Register1 Offset 0x004.
Data Fields | |
| uint32_t | b1_GpadcTrigger: 1 |
| uint32_t | b7_Nu1: 7 |
| uint32_t | b1_GpadcInit: 1 |
| uint32_t | b7_Nu2: 7 |
| uint32_t | b1_GpadcFsmBypass: 1 |
| uint32_t | b7_Nu3: 7 |
| uint32_t | b1_GpadcStartBypVal: 1 |
| uint32_t | b7_Nu4: 7 |
| uint32_t GPADCREG_REG1::b1_GpadcTrigger |
bits 0: 0
| uint32_t GPADCREG_REG1::b7_Nu1 |
bits 7: 1
| uint32_t GPADCREG_REG1::b1_GpadcInit |
bits 8: 8
| uint32_t GPADCREG_REG1::b7_Nu2 |
bits 15: 9
| uint32_t GPADCREG_REG1::b1_GpadcFsmBypass |
bits 16: 16
| uint32_t GPADCREG_REG1::b7_Nu3 |
bits 23: 17
| uint32_t GPADCREG_REG1::b1_GpadcStartBypVal |
bits 24: 24
| uint32_t GPADCREG_REG1::b7_Nu4 |
bits 31: 25