For more details and example usage, see SOC
Data Structures | |
| struct | SOC_RcmPllHsDivOutConfig |
| Structure to specific PLL HS divider output frequencies. More... | |
| struct | SOC_RcmEfuseQspiConfig |
| Efuse value for QSPI config. More... | |
Functions | |
| void | SOC_rcmCoreApllConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg) |
| Set CORE PLL Config. More... | |
| void | SOC_rcmCoreApllHSDivConfig (SOC_RcmPllHsDivOutConfig *hsDivCfg) |
| Set CORE PLL Hs Div Config. More... | |
| void | SOC_rcmDspPllConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg) |
| Set DSP PLL Config. More... | |
| void | SOC_rcmPerPllConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg) |
| Set Peripheral PLL Config. More... | |
| int32_t | SOC_rcmSetR5Clock (uint32_t r5FreqHz, uint32_t sysClkFreqHz) |
| Set R5 and SycClk frequency. More... | |
| uint32_t | SOC_rcmGetR5Clock (void) |
| Get R5 frequency. More... | |
| int32_t | SOC_rcmSetDspClock (SOC_RcmDspClockSource clkSource, uint32_t freqHz) |
| Set DSP frequency. More... | |
| uint32_t | SOC_rcmGetDspClock (void) |
| Get DSP frequency. More... | |
| int32_t | SOC_rcmSetPeripheralClock (SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, uint32_t freqHz) |
| Set peripheral frequency. More... | |
| uint32_t | SOC_rcmGetPeripheralClock (SOC_RcmPeripheralId periphId) |
| Get peripheral frequency. More... | |
| void | SOC_rcmDspPowerOnReset (void) |
| Reset Dsp Core. More... | |
| void | SOC_rcmR5PowerOnReset (void) |
| Reset R5 Core. More... | |
| void | SOC_rcmR5ConfigLockStep (void) |
| Configure R5 in lock step mode. More... | |
| void | SOC_rcmR5ConfigDualCore (void) |
| Configure R5 in dual core mode. More... | |
| void | SOC_rcmR5TriggerReset (void) |
| Trigger R5 core reset. More... | |
| void | SOC_rcmCr5bUnhalt (void) |
| Unhalt R5 core 1. More... | |
| void | SOC_rcmC66xStart (void) |
| Unhalt C66x Core. More... | |
| void | SOC_rcmGetEfuseQspiConfig (SOC_RcmEfuseQspiConfig *qspiEfuseCfg) |
| Get QSPI Efuse configuration. More... | |
| SOC_RcmResetCause | SOC_rcmGetResetCause (void) |
| Get SOC reset cause. More... | |
| void | SOC_rcmStartMemInitTCMA (void) |
| Start memory initialization for R5 TCMA. More... | |
| void | SOC_rcmWaitMemInitTCMA (void) |
| Wait memory initialization to complete for R5 TCMA. More... | |
| void | SOC_rcmStartMemInitTCMB (void) |
| Start memory initialization for R5 TCMB. More... | |
| void | SOC_rcmWaitMemInitTCMB (void) |
| Wait memory initialization to complete for R5 TCMB. More... | |
| void | SOC_rcmMemInitMssMailboxMemory (void) |
| Initialize the MSS mailbox memory. More... | |
| void | SOC_rcmMemInitDssMailboxMemory (void) |
| Initialize the DSS mailbox memory. More... | |
| void | SOC_rcmStartMemInitMSSL2 (void) |
| Start memory initialization for MSS L2. More... | |
| void | SOC_rcmWaitMemInitMSSL2 (void) |
| Wait memory initialization to complete for MSS L2. More... | |
| void | SOC_rcmStartMemInitDSSL2 (uint32_t l2bankMask) |
| Start memory initialization for DSS L2. More... | |
| void | SOC_rcmWaitMemInitDSSL2 (uint32_t l2bankMask) |
| Wait memory initialization to complete for DSS L2. More... | |
| void | SOC_rcmStartMemInitDSSL3 (uint32_t l3bankMask) |
| Start memory initialization for DSS L3. More... | |
| void | SOC_rcmWaitMemInitDSSL3 (uint32_t l3bankMask) |
| Wait memory initialization to complete for DSS L3. More... | |
| void | SOC_rcmConfigEthMacIf (void) |
| RCM configuration for MAC interface. More... | |
| uint32_t | SOC_rcmIsR5FInLockStepMode (uint32_t r5fClusterGroupId) |
| Return R5SS status operating in lockstep or dual core mode. More... | |
| void | SOC_generateSwWarmReset (void) |
| Generate SW WARM reset. More... | |
| SOC_WarmResetCause | SOC_getWarmResetCause (void) |
| Returns cause of WARM reset. More... | |
| void | SOC_clearWarmResetCause (void) |
| Clear Reset Cause register. More... | |
Macros | |
| #define | SOC_RCM_FREQ_HZ2MHZ(hz) ((hz)/(1000000U)) |
| #define | SOC_RCM_FREQ_MHZ2HZ(mhz) ((mhz)*(1000000U)) |
| #define | SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB00 (1U << 0U) |
| bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More... | |
| #define | SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB01 (1U << 1U) |
| bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More... | |
| #define | SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB10 (1U << 2U) |
| bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More... | |
| #define | SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB11 (1U << 3U) |
| bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More... | |
| #define | SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB20 (1U << 4U) |
| bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More... | |
| #define | SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB21 (1U << 5U) |
| bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More... | |
| #define | SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB30 (1U << 6U) |
| bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More... | |
| #define | SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB31 (1U << 7U) |
| bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More... | |
| #define | SOC_RCM_MEMINIT_DSSL2_MEMBANK_ALL |
| bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More... | |
| #define | SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM0 (1U << 0U) |
| bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2 More... | |
| #define | SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM1 (1U << 1U) |
| bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2 More... | |
| #define | SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM2 (1U << 2U) |
| bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2 More... | |
| #define | SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM3 (1U << 3U) |
| bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2 More... | |
| #define | SOC_RCM_MEMINIT_DSSL3_MEMBANK_ALL |
| bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2 More... | |
| #define | SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_0 (1U << 0U) |
| HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig. More... | |
| #define | SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_1 (1U << 1U) |
| HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig. More... | |
| #define | SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_2 (1U << 2U) |
| HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig. More... | |
| #define | SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_3 (1U << 3U) |
| HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig. More... | |
| #define | SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL |
| HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig. More... | |
| #define | SOC_RCM_PLL_HSDIV_OUTPUT_COUNT (4U) |
SOC Warm Reset Causes | |
| enum | SOC_WarmResetCause { SOC_WarmResetCause_POWER_ON_RESET = 0x09U, SOC_WarmResetCause_MSS_WDT = 0x0AU, SOC_WarmResetCause_TOP_RCM_WARM_RESET_CONFIG = 0x0CU, SOC_WarmResetCause_EXT_PAD_RESET = 0x08U, SOC_WarmResetCause_HSM_WDT = 0x18U } |
| #define SOC_RCM_FREQ_HZ2MHZ | ( | hz | ) | ((hz)/(1000000U)) |
| #define SOC_RCM_FREQ_MHZ2HZ | ( | mhz | ) | ((mhz)*(1000000U)) |
| #define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB00 (1U << 0U) |
bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2
| #define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB01 (1U << 1U) |
bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2
| #define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB10 (1U << 2U) |
bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2
| #define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB11 (1U << 3U) |
bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2
| #define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB20 (1U << 4U) |
bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2
| #define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB21 (1U << 5U) |
bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2
| #define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB30 (1U << 6U) |
bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2
| #define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB31 (1U << 7U) |
bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2
| #define SOC_RCM_MEMINIT_DSSL2_MEMBANK_ALL |
bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2
| #define SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM0 (1U << 0U) |
bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2
| #define SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM1 (1U << 1U) |
bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2
| #define SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM2 (1U << 2U) |
bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2
| #define SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM3 (1U << 3U) |
bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2
| #define SOC_RCM_MEMINIT_DSSL3_MEMBANK_ALL |
bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2
| #define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_0 (1U << 0U) |
HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig.
| #define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_1 (1U << 1U) |
HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig.
| #define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_2 (1U << 2U) |
HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig.
| #define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_3 (1U << 3U) |
HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig.
| #define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL |
HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig.
| #define SOC_RCM_PLL_HSDIV_OUTPUT_COUNT (4U) |
| enum SOC_WarmResetCause |
| enum SOC_RcmResetCause |
Reset Causes.
| enum SOC_RcmPeripheralId |
Peripheral IDs.
Peripheral Clock Sources.
DSP Clock Sources.
| enum SOC_RcmR5ClockSource |
| enum SOC_RcmPllFoutFreqId |
PLL Fout values.
| void SOC_rcmCoreApllConfig | ( | SOC_RcmPllFoutFreqId | outFreqId, |
| SOC_RcmPllHsDivOutConfig * | hsDivCfg | ||
| ) |
Set CORE PLL Config.
| outFreqId | [in] Output frequency form the PLL |
| hsDivCfg | [in] Set HS divider output frequencies |
| void SOC_rcmCoreApllHSDivConfig | ( | SOC_RcmPllHsDivOutConfig * | hsDivCfg | ) |
Set CORE PLL Hs Div Config.
| hsDivCfg | [in] Set HS divider output frequencies |
| void SOC_rcmDspPllConfig | ( | SOC_RcmPllFoutFreqId | outFreqId, |
| SOC_RcmPllHsDivOutConfig * | hsDivCfg | ||
| ) |
Set DSP PLL Config.
| outFreqId | [in] Output frequency form the PLL |
| hsDivCfg | [in] Set HS divider output frequencies |
| void SOC_rcmPerPllConfig | ( | SOC_RcmPllFoutFreqId | outFreqId, |
| SOC_RcmPllHsDivOutConfig * | hsDivCfg | ||
| ) |
Set Peripheral PLL Config.
| outFreqId | [in] Output frequency form the PLL |
| hsDivCfg | [in] Set HS divider output frequencies |
| int32_t SOC_rcmSetR5Clock | ( | uint32_t | r5FreqHz, |
| uint32_t | sysClkFreqHz | ||
| ) |
Set R5 and SycClk frequency.
| r5FreqHz | [in] R5 frequency, in Hz |
| sysClkFreqHz | [in] SysClk frequency, in Hz |
| uint32_t SOC_rcmGetR5Clock | ( | void | ) |
Get R5 frequency.
| int32_t SOC_rcmSetDspClock | ( | SOC_RcmDspClockSource | clkSource, |
| uint32_t | freqHz | ||
| ) |
Set DSP frequency.
| clkSource | [in] DSP clock source to use |
| freqHz | [in] DSP frequency, in Hz |
| uint32_t SOC_rcmGetDspClock | ( | void | ) |
Get DSP frequency.
| int32_t SOC_rcmSetPeripheralClock | ( | SOC_RcmPeripheralId | periphId, |
| SOC_RcmPeripheralClockSource | clkSource, | ||
| uint32_t | freqHz | ||
| ) |
Set peripheral frequency.
| periphId | [in] Peripheral ID |
| clkSource | [in] Peripheral clock source to use |
| freqHz | [in] Peripheral frequency, in Hz |
| uint32_t SOC_rcmGetPeripheralClock | ( | SOC_RcmPeripheralId | periphId | ) |
Get peripheral frequency.
| periphId | [in] Peripheral ID |
| void SOC_rcmDspPowerOnReset | ( | void | ) |
Reset Dsp Core.
| void SOC_rcmR5PowerOnReset | ( | void | ) |
Reset R5 Core.
| void SOC_rcmR5ConfigLockStep | ( | void | ) |
Configure R5 in lock step mode.
| void SOC_rcmR5ConfigDualCore | ( | void | ) |
Configure R5 in dual core mode.
| void SOC_rcmR5TriggerReset | ( | void | ) |
Trigger R5 core reset.
| void SOC_rcmCr5bUnhalt | ( | void | ) |
Unhalt R5 core 1.
| void SOC_rcmC66xStart | ( | void | ) |
Unhalt C66x Core.
| void SOC_rcmGetEfuseQspiConfig | ( | SOC_RcmEfuseQspiConfig * | qspiEfuseCfg | ) |
Get QSPI Efuse configuration.
| qspiEfuseCfg | [out] QSPI Efuse configuration |
| SOC_RcmResetCause SOC_rcmGetResetCause | ( | void | ) |
Get SOC reset cause.
| void SOC_rcmStartMemInitTCMA | ( | void | ) |
Start memory initialization for R5 TCMA.
| void SOC_rcmWaitMemInitTCMA | ( | void | ) |
Wait memory initialization to complete for R5 TCMA.
| void SOC_rcmStartMemInitTCMB | ( | void | ) |
Start memory initialization for R5 TCMB.
| void SOC_rcmWaitMemInitTCMB | ( | void | ) |
Wait memory initialization to complete for R5 TCMB.
| void SOC_rcmMemInitMssMailboxMemory | ( | void | ) |
Initialize the MSS mailbox memory.
| void SOC_rcmMemInitDssMailboxMemory | ( | void | ) |
Initialize the DSS mailbox memory.
| void SOC_rcmStartMemInitMSSL2 | ( | void | ) |
Start memory initialization for MSS L2.
| void SOC_rcmWaitMemInitMSSL2 | ( | void | ) |
Wait memory initialization to complete for MSS L2.
| void SOC_rcmStartMemInitDSSL2 | ( | uint32_t | l2bankMask | ) |
Start memory initialization for DSS L2.
| void SOC_rcmWaitMemInitDSSL2 | ( | uint32_t | l2bankMask | ) |
Wait memory initialization to complete for DSS L2.
| void SOC_rcmStartMemInitDSSL3 | ( | uint32_t | l3bankMask | ) |
Start memory initialization for DSS L3.
| void SOC_rcmWaitMemInitDSSL3 | ( | uint32_t | l3bankMask | ) |
Wait memory initialization to complete for DSS L3.
| void SOC_rcmConfigEthMacIf | ( | void | ) |
RCM configuration for MAC interface.
| uint32_t SOC_rcmIsR5FInLockStepMode | ( | uint32_t | r5fClusterGroupId | ) |
Return R5SS status operating in lockstep or dual core mode.
| r5fClusterGroupId | [in] R5F Cluster Group Id. Refer CSL_ArmR5ClusterGroupID for applicable values. |
| void SOC_generateSwWarmReset | ( | void | ) |
Generate SW WARM reset.
| SOC_WarmResetCause SOC_getWarmResetCause | ( | void | ) |
Returns cause of WARM reset.
| void SOC_clearWarmResetCause | ( | void | ) |
Clear Reset Cause register.