Register Offset 0x000.
Data Fields | |
| uint32_t | b2_DcbistMode: 2 |
| uint32_t | b6_Nu1: 6 |
| uint32_t | b1_GpadcFsmClkEnable: 1 |
| uint32_t | b3_Gpadc2adcbufPathEn: 3 |
| uint32_t | b4_Nu2: 4 |
| uint32_t | b1_GpadcDebugModeEnable: 1 |
| uint32_t | b15_Nu3: 15 |
| uint32_t GPADCREG_REG0::b2_DcbistMode |
bits 1: 0
| uint32_t GPADCREG_REG0::b6_Nu1 |
bits 7: 2
| uint32_t GPADCREG_REG0::b1_GpadcFsmClkEnable |
bits 8: 8
| uint32_t GPADCREG_REG0::b3_Gpadc2adcbufPathEn |
bits 11: 9
| uint32_t GPADCREG_REG0::b4_Nu2 |
bits 15: 12
| uint32_t GPADCREG_REG0::b1_GpadcDebugModeEnable |
bits 16: 16
| uint32_t GPADCREG_REG0::b15_Nu3 |
bits 31: 17